The present invention relates to integrated circuit structures and fabrication methods.
Background: Parasitic Capacitance of Interconnects
The performance of current interconnect systems is becoming limited by the system interconnect delay. This is recognized as being a major unresolved challenge to the semiconductor industry. A major component of this delay results from intralevel capacitance. Parasitic capacitance of conductors hurts performance in at least two ways: first, the distributed capacitive load on wiring will slow down the propagation of signals. Secondly, the capacitive coupling between adjacent lines can cause "cross-talk," where a pulse on one line is coupled into an adjacent line. This can lead to unpredictable logic errors.
Parasitic capacitance can be reduced by using insulation with a lower dielectric constant k. Currently, low k dielectric materials (e.g. HSQ k=2.8; parylene 2.4; aerogel 1.7 etc.) are used for gap fill and inter-metal dielectrics.
Background: Step Coverage and Void Formation
FIGS. 4A-4C show how undesired voids can be accidentally formed in the prior art. Since deposition tends to be more rapid on the exposed edges 402 of adjacent lines 400, the thicker accumulations of material 410 deposited on these edges 402 can eventually meet to enclose a void 404. This has long been recognized as a problem.
Background: Air Bridge Structures
"Air bridge" structures have been used in the past in microwave circuits, to minimize vertical capacitive coupling where one line crosses over another. However, there has been no way to adapt this technology to reduce capacitance between very long parallel signal lines. Air bridges are discussed, for example, in the following references, all of which are hereby incorporated by reference: Tsai et al., "Multiple arbitrary shape via-hole and air-bridge transitions in multilayered structures," 1996 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST vol.2, p.707-10 (1996); Villeneuve et al., "Air-bridge microcavities, " APPLIED PHYSICS LETTERS, vol.67, no.2, p. 167-9 (Jul. 10, 1995); and Goldfarb et al., "The effect of air bridge height on the propagation characteristics of microstrip," 1 IEEE MICROWAVE AND GUIDED WAVE LETTERS 273 (October 1991).
Innovative Structure and Method
The present application discloses an ultimate low k (k=1) gap structure for high speed logic devices in which the sidewalls fully or partially cover the gaps between the interconnects by dry etching the already formed aluminum interconnects after the photoresist has been stripped. The present application also discloses a particularly surprising method of fabricating lateral air gaps using the insulating sidewalls which normally form on conductors during anisotropic plasma etching. This is done by using a sacrificial layer on which the sidewall is formed, and then removing the sacrificial layer, so that residual mechanical stress will cause the free standing portion of the sidewall layer to curve outward from the patterned conductor layer. Adjacent lines of such curling sidewall material will then form arches, which provide a partial template for subsequent deposition of an insulator, such as silicon dioxide, which will encapsulate the air gap between the adjacent conductors.
The innovative structure and method of the present invention provides the following advantages:
reduced parasitic capacitance between parallel conductors; PA1 no new equipment or process is required; PA1 better suited for narrower gaps; PA1 substantially no solid dielectric is formed on the sidewalls of the metal lines; PA1 air gap height is only slightly greater than that of the metal line, hence the interlevel dielectric layer thickness is not excessive; and PA1 air gap scales with reduction in metal pitch.